Integration of inductors on a chip within a BiCMOS process makes possible the realization of transceivers on a single chip. Single-ended or differential cascode architectures with an inductive load and inductive degeneration have been successfully integrated to produce LNAs and mixers. Typical schemes of these functional circuits relative to the production of an LNA are shown in FIGS. 1a and 1b whereas the schemes of FIGS. 2a and 2b relate to the mixer. For both applications, the figures show a single-ended architecture and a differential architecture.
Inductive degeneration of a low noise input transistor or pair of input transistors (Q1, Q3, Q4), which are commonly NPN bipolar junction transistors because of the low noise requisite, offers considerable advantages compared to a traditional resistive degeneration (in integrated circuits). Inductive degeneration introduces less noise, enhances linearity, while the inductive load, formed by a functional circuit driven in a current mode by the input transistor or pair of transistors, that in all the figures is represented by a generic oscillating circuit, permits a voltage swing on the output node that may exceed the value of the supply voltage (Vdd) of the circuit.
A broad range of dynamic excursion of the signals, an improved linearity and a good low noise performance may be usually obtained at the expense of comparably increased current absorption levels. To ensure an adequate control of the noise profile, gain and input impedance, the circuit should have a bias circuit with characteristics of high precision and low noise.
Substantially, the problem of biasing an amplifier or a mixer or any other low noise functional cascode circuit with a single or differential termination requires, in practice, biasing the transistor or each of the two transistors that make up the pair of bipolar input transistors, at the augmented level. A solution of the problem is not straightforward because of a number of effects that must be taken into account, namely: the influence on the current across the input transistor due to the spread of the parasitic resistance associated to the integrated inductor Le of degeneration; the noise contribution of the bias circuit; the dependence of the performances of the functional circuit, i.e. voltage gain, input impedance and noise profile, from the collector's bias current in the input transistor or input transistors; the fact that the collector of the input transistor (or of a second transistor in case of a cascode configuration) is at the supply voltage and thereby a feedback control of the collector's current cannot be used because introduction of a current sensor is not possible.
If the input transistor is driven in a voltage mode, the spread of the emitter's potential of the transistor will considerably and unpredictably reduce the bias current due to the exponential relationship between Vb and the collector's current Ic. Unfortunately, there is not an easy way to determine with precision the variation of the parasitic resistance Re of the integrated inductor Le of degeneration, unless a replica of the inductor is included in the biasing circuit. However, this would cause an increment of power consumption and require additional area of integration.
Moreover, the bias circuit should not significantly contribute to noise generation and increase the noise profile of the functional circuit, nor modify the input impedance. Therefore, the only way is to deliver the base bias current Ib through a DC path, for example an integrated biasing resistor Rb that notably has a typical thermal noise current of about 4 kT/Rb. This noise contribution adds directly to the input current noise of the functional circuit and should be compared to 2q*Ib, which represents the shot noise current density associated to the current Ib. Hence: EQU Inoise=2q*Ib+4 kT/Rb=2q*Ib(I+50 mv/Rb*Ib)
Rb should be thoroughly sized because the bias circuit should be in a condition to supply a higher base current Ib.sub.high under low gain conditions of current (where Ib.sub.high =3*Ib.sub.low). This means that the use of a correctly dimensioned physically integrated resistor Rb should establish: EQU Rb*Ib.sub.high =.DELTA.V
and therefore: EQU Rb*Iblow=.DELTA.V/3
In traditional circuits with resistive degeneration it is common to alleviate these problems with a feedback control by introducing a sensor, such as for example a resistance, between the collector and the supply node or between the emitter and the ground node (or vice versa in the case of a circuit with inverted polarities). The feedback loop senses the value of the collector current Ic or of the emitter current Le and regulates the base potential Vbe (or the base bias current Ib) accordingly. This approach cannot be used in the above-considered situation because the collector of the input transistor Q1 is at the supply voltage while the emitter operates at an unknown potential.
Another known approach is to use a current mirror which may be suitable when the potential of the emitter is well defined (and reproducible) and therefore there is no need to isolate the biasing circuit from the functional circuit. Even this approach is inapplicable to the above-considered case.
An improved scheme is illustrated in FIG. 3. According to this scheme, the ratio DVc/Ic due to the variation of the emitter's potential is reduced, decoupling simultaneously the functional circuit from the biasing circuit with the resistance Rb. Although this scheme is better than the more traditional scheme based on the use of a current mirror, it still does not fully meet the above-mentioned requirements because: the collector current depends on the value of Re; the permitted voltage drop on Rb is Vdt-Vds-Vbe.congruent.Vdd-Vth-Vbe, therefore noise contribution is not effectively minimized.